1. Field of the Invention
The present invention relates to a dielectric separate type semiconductor device aiming at a higher withstand voltage of semiconductor elements isolated by a dielectric region.
2. Description of the Related Art
In the field of integrated circuits containing semiconductor elements handling high voltage and large current, or so-called power IC and high withstand voltage IC, in order to avoid mutual effects of actions of individual elements, it is effective to separate the elements by means of a dielectric. Such examples include, among others, an SOI substrate in which two silicon substrates are bonded together through an insulating film, bonded firmly, and a silicon layer of a desired thickness is formed by polishing, and a SIMOX substrate in which oxygen ions are injected into a silicon substrate to be treated at high temperature, and a silicon dioxide film (hereinafter called an oxide film) is formed at a position of a specific depth from the surface. In such SOI substrates and SIMOX substrates, in order to separate the elements further in the lateral direction, another insulator region is formed to enclose the elements and reach the insulating film inside the substrate, thereby realizing an IC in which individual element regions are completely isolated by dielectric materials.
On the other hand, in the SOI substrate, by the insulating film formed inside (hereinafter called a buried insulating film), the substrate face side, that is, the element forming region, and the substrate back side are electrically isolated, but in order to hold the withstand voltage of an element, it is generally known to fix the potential of the substrate.
An example of high withstand voltage elements formed on an SOI substrate is described below. FIG. 1 is a simplified plan view of a MOSFET isolated by a dielectric region. In an element forming region 20 enclosed by a trench isolation region 4, a drain field 1, a source field 2, and a gate polysilicon film 3 are disposed, and in order to obtain a high withstand voltage, the drain field 1 is placed at a position remote from the edge of the gate polysilicon film 3.
FIG. 2 is a sectional view along line A--A of the MOSFET shown in FIG. 1, showing together a mode of depletion region when an inverse bias is applied between the drain and source. In an SOI layer 16 of an SOI substrate 17 consisting of a first silicon substrate (p.sup.- type) 14, a buried oxide film layer 12, and a second silicon substrate (p.sup.- type) 15, a P channel MOSFET is formed. The SOI layer 16 is isolated into elements by a trench isolation region 4 in which an element isolating oxide film 13 is buried, and a p.sup.- drain diffusion layer 10, a p.sup.+ source diffusion layer 6, and an n.sup.+ back gate diffusion layer 7 are formed in a n.sup.- diffusion layer 11 reaching down to the buried oxide film 12, and further a p.sup.+ drain diffusion layer 5 is formed in the p.sup.- drain diffusion layer 10. Moreover, through a gate oxide film 9, a gate polysilicon film 3 is formed so as to ride on a field oxide film 8.
In such a P channel MOSFET, the withstand voltage between the source and drain is determined by the junction withstand voltage between the p.sup.- drain diffusion layer 10 and n.sup.- diffusion layer 11, but by applying the same bias as in the drain to the SOI substrate back side 19, a higher withstand voltage than the junction withstand voltage may be realized. More specifically, setting the drain electrode (not shown) connected to the p.sup.+ drain diffusion layer 5 and the back electrode (not shown) connected to the SOI substrate back side 19 at the ground potential, when a positive potential is applied to the source electrode (not shown) connected between the p.sup.+ source diffusion layer 6 and n.sup.+ back gate diffusion layer 7, and the gate electrode (not shown) connected to the gate polysilicon film 3, a depletion layer spreads in the junction of the p.sup.- drain diffusion layer 10 and n.sup.- diffusion layer 11, and a diffusion layer also spreads in the n.sup.- diffusion layer 11 on the buried oxide film 12. By further raising the potential, the two depletion layers are joined together, and a depletion region 18 is formed. Thus, as the depletion layers are joined, the electric field at the junction of the p.sup.- drain diffusion layer 10 and n.sup.- diffusion layer 11 is alleviated, so that a higher withstand voltage than the intrinsic junction withstand voltage is realized.
However, in the conventional high withstand voltage elements, it is required to apply a ground potential to the SOI substrate back side. A silicon chip forming an IC is usually sealed with a resin, and is processed so that terminals connected to the electrodes on the silicon chip are drawn out to the outside of the resin, and in this case terminals connected to the back side of the silicon chip are required. In the case of an ordinary mold package, it is possible by connecting the silicon chip back side and lead frame electrically by using a conductive material, and taking out the terminals outside of the resin. Recently, however, as the electronic appliances are becoming smaller in size and lighter in weight, the IC can be mounted by various mounting methods such as chip on board (COB) and chip on film (COF), and terminals connected to the chip back side cannot be always provided easily. Nevertheless, in the structure of such conventional high withstand voltage elements, the withstand voltage of elements deteriorates unless a ground potential is applied to the SOI substrate back side.